Exemplary embodiments of this invention relate to output buffer circuits and electrical systems including output buffer circuits.
Generally, a semiconductor integrated circuit includes an output buffer circuit that outputs a signal produced by the semiconductor integrated circuit through an output terminal. Various techniques are proposed to suppress overshoot and undershoot that may be generated in the signal outputted by the output buffer circuit.
FIG. 6 shows a conventional output buffer circuit in which overshoot and undershoot are suppressed.
An output buffer circuit 100 shown in FIG. 6 includes a P-channel output transistor 11 having a source S to which VDD potential is supplied and a drain D connected to an output terminal 22. Output buffer circuit 100 also includes an N-channel output transistor 12 having a source S to which GND potential is supplied and a drain D connected to output terminal 22.
Output buffer circuit 100 further includes capacitor elements 19 and 20, each having a first terminal connected to output terminal 22.
Further, output buffer circuit 100 includes inverters 17 and 18. Inverter 17 controls P-channel output transistor 11 by changing the potential of a gate G of P-channel output transistor 11. Inverter 18 controls N-channel output transistor 12 by changing the potential of a gate G of N-channel output transistor 12. In output buffer circuit 100 thus constructed, overshoot and undershoot are suppressed as further explained below.
Initially, an input signal A is assumed to be in ‘L’ level. Accordingly, both inverters 17 and 18 output ‘H’ level signals, and both node N1 (e.g., gate of P-channel output transistor 11) and node N2 (e.g., gate of N-channel output transistor 12) are in ‘H’ level. Because ‘H’ level signal is supplied to each of gates G of P-channel output transistor 11 and N-channel output transistor 12, P-channel output transistor 11 and N-channel output transistor 12 are in OFF- and ON-states, respectively. Accordingly, an output signal B1 at output terminal 22 is in ‘L’ level.
Then, input signal A changes from ‘L’ level to ‘H’ level. As a result, levels of both nodes N1 and N2 change to ‘L’ level. Accordingly, P-channel output transistor 11 and N-channel output transistor 12 change to ON- and OFF-states, respectively, and output signal B1 changes from ‘L’ level to ‘H’ level. Here, because capacitor element 19 is provided between output terminal 22 and node N1, overshoot generated when output signal B1 changes to ‘H’ level is fed back through capacitor element 19 to node N1. As a result, the overshoot is suppressed.
Next, input signal A changes from ‘H’ level to ‘L’ level. As a result, both nodes N1 and N2 change to ‘H’ level. Accordingly, P-channel output transistor 11 and N-channel output transistor 12 change to OFF- and ON-states, respectively, and output signal B1 changes from ‘H’ to ‘L’ level. Here, because capacitor element 20 is provided between output terminal 22 and node N2, undershoot generated when output signal B1 changes to ‘L’ level is fed back through capacitor element 20 to node N2. As a result, the undershoot is suppressed.
A CMOS output buffered circuit that utilizes such technique to suppress overshoot and undershoot is proposed in, for example, U.S. Pat. No. 5,121,000 to Naghshineh.
However, the technique disclosed in Naghshineh is deficient for the following reasons.
During a period when input signal A is in ‘L’ level, node N1 is in ‘H’ level, and output signal B1 is in ‘L’ level. Thus, a voltage corresponding to the difference between ‘H’ and ‘L’ levels is applied between the terminals of capacitor element 19. Accordingly, electrical charge corresponding to the voltage is stored in capacitor element 19. Thereafter, although node N1 starts to change from ‘H’ level to ‘L’ level when input signal A changes from ‘L’ level to ‘H’ level, a time to discharge the charge stored in capacitor element 19 is required before node N1 changes to ‘L’ level. As a result, change of the level of node N1 from ‘H’ to ‘L’ level is delayed during the time required to discharge the charge stored in capacitor element 19. Similarly, although node N2 starts to change from ‘L’ to ‘H’ level when input signal A changes from ‘H’ to ‘L’ level, a time to discharge the charge stored in capacitor element 20 is required before node N2 changes to ‘H’ level. As a result, change of the level of node N2 from ‘L’ to ‘H’ level is delayed during the time required to discharge the charge stored in capacitor element 20.
Accordingly, the timing of output signal B1 is delayed, and the slew rate of output signal B1 is degraded.